Design and development of computing-in-memory (cim) architecture with a non-volatile one-time programmable read-only memory (otp-rom) using skywater 130nm pdk for edge ai applications/
Alcanzo, John Praxie B.
Design and development of computing-in-memory (cim) architecture with a non-volatile one-time programmable read-only memory (otp-rom) using skywater 130nm pdk for edge ai applications/ John Praxie B. Alcanzo, Abraham Abalos, Aedrian Carl Bayle, Joachim Lowe Z. Gonzales, Edward Gustav G. Negre, and Christian Dave B. Perez.-- - Manila: Technological University of the Philippines, 2025. - xi, 87pages: 29cm.
Bachelor's thesis
College of Engineering.--
Includes bibliographic references and index.
The importance of real-time AI processing for edge devices is increasing. has
trouble with the von Neumann bottleneck, which reduces how much data can be transferred
balance between the speed of memory and the processing power of the computer. The work
focuses on a Computing-in approach. Architecture that combines Memory (CiM) and Non-
Volatile One-Time Programmable. In SkyWater 130-nm PDK, using Read-Only Memory
(OTP-ROM), to lower data. compute and store information on the same memory chip at
the same time.
At the beginning, the approach concentrates on checking prior works to assess if
CiM resolves the von Neumann bottleneck and helps machine learning by using SRAM-
based models. The researchers also make use of SkyWater’s 130 nm PDK to design and
construct a CiM system, which has a non-volatile one-time programmable (OTP) read-only
memory (ROM) to ensure the scalability and stability of the system. Experimental testing
proves that the architecture is suitable by ensuring data preserves, programming works
well, and power usage is low in various weather scenarios. Collecting these data is meant
to highlight how CiM is beneficial in practice.
Arithmetic logic units, CiM core with OTP-ROM, SRAM-based processing parts,
and an improved control unit define the design. Operating at 10 MHz with 8-bit inputs, the
system achieves a throughput of 0.04096 TOPS, an energy efficiency of 29.68 TOPS/W
based on a power consumption of 1.38 mW at 1.8 V, and an area efficiency of 3.09 ×
10−14 TOPS/nm2 using a silicon area of 1098 μm × 1206 μm. These findings show above
conventional architectures enhanced throughput, energy efficiency, and space efficiency.
Engineering
One-time programmable
Read-only memory (rom)
BTH TK 870 / A43 2025
Design and development of computing-in-memory (cim) architecture with a non-volatile one-time programmable read-only memory (otp-rom) using skywater 130nm pdk for edge ai applications/ John Praxie B. Alcanzo, Abraham Abalos, Aedrian Carl Bayle, Joachim Lowe Z. Gonzales, Edward Gustav G. Negre, and Christian Dave B. Perez.-- - Manila: Technological University of the Philippines, 2025. - xi, 87pages: 29cm.
Bachelor's thesis
College of Engineering.--
Includes bibliographic references and index.
The importance of real-time AI processing for edge devices is increasing. has
trouble with the von Neumann bottleneck, which reduces how much data can be transferred
balance between the speed of memory and the processing power of the computer. The work
focuses on a Computing-in approach. Architecture that combines Memory (CiM) and Non-
Volatile One-Time Programmable. In SkyWater 130-nm PDK, using Read-Only Memory
(OTP-ROM), to lower data. compute and store information on the same memory chip at
the same time.
At the beginning, the approach concentrates on checking prior works to assess if
CiM resolves the von Neumann bottleneck and helps machine learning by using SRAM-
based models. The researchers also make use of SkyWater’s 130 nm PDK to design and
construct a CiM system, which has a non-volatile one-time programmable (OTP) read-only
memory (ROM) to ensure the scalability and stability of the system. Experimental testing
proves that the architecture is suitable by ensuring data preserves, programming works
well, and power usage is low in various weather scenarios. Collecting these data is meant
to highlight how CiM is beneficial in practice.
Arithmetic logic units, CiM core with OTP-ROM, SRAM-based processing parts,
and an improved control unit define the design. Operating at 10 MHz with 8-bit inputs, the
system achieves a throughput of 0.04096 TOPS, an energy efficiency of 29.68 TOPS/W
based on a power consumption of 1.38 mW at 1.8 V, and an area efficiency of 3.09 ×
10−14 TOPS/nm2 using a silicon area of 1098 μm × 1206 μm. These findings show above
conventional architectures enhanced throughput, energy efficiency, and space efficiency.
Engineering
One-time programmable
Read-only memory (rom)
BTH TK 870 / A43 2025