MARC details
| 000 -LEADER |
| fixed length control field |
02149nam a22003735i 4500 |
| 001 - CONTROL NUMBER |
| control field |
20898504 |
| 003 - CONTROL NUMBER IDENTIFIER |
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
| control field |
20240805104731.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
| fixed length control field |
190321s2019 nju 000 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
| LC control number |
2019937605 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
| International Standard Book Number |
9780135732410 (pbk. : alk. paper) |
| 040 ## - CATALOGING SOURCE |
| Original cataloging agency |
DLC |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
TUPM |
| 042 ## - AUTHENTICATION CODE |
| Authentication code |
pcc |
| 050 #0 - LIBRARY OF CONGRESS CALL NUMBER |
| Classification number |
TK 7874.75 |
| Item number |
D55 2019 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
| Personal name |
Dillinger, Thomas E. |
| 245 00 - TITLE STATEMENT |
| Title |
Vlsi design methodology development / |
| Statement of responsibility, etc. |
Thomas E. Dillinger. |
| 250 ## - EDITION STATEMENT |
| Edition statement |
1st edition. |
| 263 ## - PROJECTED PUBLICATION DATE |
| Projected publication date |
1907 |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
| Place of production, publication, distribution, manufacture |
Hoboken, NJ : |
| Name of producer, publisher, distributor, manufacturer |
Pearson Education, Inc., |
| Date of production, publication, distribution, manufacture, or copyright notice |
2019. |
| 300 ## - PHYSICAL DESCRIPTION |
| Extent |
xvii, 734 pages : |
| Other physical details |
illustrations ; |
| Dimensions |
24 cm |
| 336 ## - CONTENT TYPE |
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
| Media type term |
unmediated |
| Media type code |
n |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
| Carrier type term |
volume |
| Carrier type code |
nc |
| Source |
rdacarrier |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
| Bibliography, etc. note |
Includes index and bibliographical references |
| 505 0# - FORMATTED CONTENTS NOTE |
| Formatted contents note |
Introduction VLSI Design methodology Hierarchical design decomposition Cell and IP modeling Characteristics of functional validation Characteristics of formal equivalency verification Logic synthesis Placement Routing Layout parasitic extraction and electrical modeling Timing analysis Noise analysis Power analysis Power rail voltage drop analysis Electromigration (EM) reliability analysis Miscellaneous electrical analysis requirements ECOs Physical design verification Design for testability analysis Preparation for tapeout Post-silicon debug and characterization ("bring-up") and product qualification |
| 520 ## - SUMMARY, ETC. |
| Summary, etc. |
As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. |
| 650 10 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| 650 10 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name entry element |
Integrated circuits |
| 650 10 - SUBJECT ADDED ENTRY--TOPICAL TERM |
| Topical term or geographic name entry element |
Microelectronics |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
| a |
0 |
| b |
ibc |
| c |
orignew |
| d |
2 |
| e |
epcn |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
| Source of classification or shelving scheme |
Library of Congress Classification |
| Koha item type |
Book |