000			03148nam a22003377a 4500
003			OSt
005			20250715172141.0
008			250715b |||||||| |||| 00| 0 eng d
040			_aTUPM _bEnglish _cTUPM _dTUPM _erda
050			_aBTH TK 870 _bA43 2025
100			_aAlcanzo, John Praxie B. _eauthor
245			_aDesign and development of computing-in-memory (cim) architecture with a non-volatile one-time programmable read-only memory (otp-rom) using skywater 130nm pdk for edge ai applications/ _cJohn Praxie B. Alcanzo, Abraham Abalos, Aedrian Carl Bayle, Joachim Lowe Z. Gonzales, Edward Gustav G. Negre, and Christian Dave B. Perez.--
260			_aManila: _bTechnological University of the Philippines, _c2025.
300			_axi, 87pages: _c29cm.
336			_2rdacontent
337			_2rdamedia
338			_2rdacarrier
500			_aBachelor's thesis
502			_aCollege of Engineering.-- _bBachelor of science in electronics engineering: _cTechnological University of the Philippines, _d2025.
504			_aIncludes bibliographic references and index.
520			_aThe importance of real-time AI processing for edge devices is increasing. has trouble with the von Neumann bottleneck, which reduces how much data can be transferred balance between the speed of memory and the processing power of the computer. The work focuses on a Computing-in approach. Architecture that combines Memory (CiM) and Non- Volatile One-Time Programmable. In SkyWater 130-nm PDK, using Read-Only Memory (OTP-ROM), to lower data. compute and store information on the same memory chip at the same time. At the beginning, the approach concentrates on checking prior works to assess if CiM resolves the von Neumann bottleneck and helps machine learning by using SRAM- based models. The researchers also make use of SkyWater’s 130 nm PDK to design and construct a CiM system, which has a non-volatile one-time programmable (OTP) read-only memory (ROM) to ensure the scalability and stability of the system. Experimental testing proves that the architecture is suitable by ensuring data preserves, programming works well, and power usage is low in various weather scenarios. Collecting these data is meant to highlight how CiM is beneficial in practice. Arithmetic logic units, CiM core with OTP-ROM, SRAM-based processing parts, and an improved control unit define the design. Operating at 10 MHz with 8-bit inputs, the system achieves a throughput of 0.04096 TOPS, an energy efficiency of 29.68 TOPS/W based on a power consumption of 1.38 mW at 1.8 V, and an area efficiency of 3.09 × 10−14 TOPS/nm2 using a silicon area of 1098 μm × 1206 μm. These findings show above conventional architectures enhanced throughput, energy efficiency, and space efficiency.
650			_aEngineering
650			_aOne-time programmable
650			_aRead-only memory (rom)
700			_aAbalos, Abraham _eauthor
700			_aBayle, Aedrian Carl _eauthor
700			_aGonzales, Joachim Lowe Z. _eauthor
700			_aNegre, Edward Gustav G. _eauthor
700			_aPerez, Christian Dave B. _eauthor
942			_2lcc _cBTH COE _n0
999			_c30368 _d30368