000			03371nam a22003377a 4500
003			OSt
005			20250718150339.0
008			250718b |||||||| |||| 00| 0 eng d
040			_aTUPM _bEnglish _cTUPM _dTUPM _erda
050			_aBTH TK 870 _bA33 2025
100			_aAdan, Rafael Carlos M. _eauthor
245			_aDesign of pvt (process, voltage, and temperature) variation- less i/o buffer using skywater 130nm cmos (complementary metal-oxide-semiconductor) process for usb (universal serial bus) applications/ _cRafael Carlos M. Adan, Mherby C. Almarinez, Dawn Gabrielle D. Angkahan, Laureana Joy S. Banao, Froilan Arnel M. Dela Cruz, and John Christian Z. Leocario.--
260			_aManila: _bTechnological University of the Philippines, _c2025.
300			_axiii, 171pages: _c29cm.
336			_2rdacontent
337			_2rdamedia
338			_2rdacarrier
500			_aBachelor's thesis
502			_aCollege of Engineering.-- _bBachelor of science in electronics engineering: _cTechnological University of the Philippines, _d2025.
504			_aIncludes bibliographic references and index.
520			_aThis paper presents the design of a Process, Voltage, and Temperature (PVT) variation-resilient Input/Output (I/O) buffer using the Skywater 130nm CMOS technology for USB applications. PVT variations often degrade I/O buffer performance, affecting signal integrity, power efficiency, and reliability. To address these challenges, the proposed design integrates PVT detection and compensation techniques, ensuring consistent operation under fluctuating conditions. The buffer supports a maximum data rate of 50 MHz and achieves a data throughput of 100 Mbps. Silicon measurement results confirm reliable operation at a load capacitance of 20 pF and VDDIO supply voltages of 1.8V and 2.5V. The analysis of the compensated and uncompensated circuits reveals a clear advantage for the compensated design. The compensated circuit achieved a higher mean slew rate of 1.1352 V/ns compared to 0.9439 V/ns for the uncompensated circuit, indicating an improved dynamic response. Furthermore, the distribution of slew rates in the compensated circuit is more tightly clustered around the optimal range of 1.0–1.2 V/ns, as evidenced by a lower standard deviation of 0.2386 V/ns versus 0.2784 V/ns in the uncompensated circuit. This consistent performance highlights the effectiveness of the compensation techniques implemented in the design maintaining stability across various PVT variations. The buffer’s architecture offers a robust and power-aware solution suitable for high-speed digital interfaces, particularly in systems where maintaining data integrity under variable environmental and manufacturing conditions is critical. This work contributes a practical and efficient approach to designing reliable I/O buffers for modern integrated circuits, especially in USB and other high-speed communication domains where PVT robustness is increasingly essential.
650			_aI/O buffer design
650			_aPVT compensation
650			_aCMOS technology
700			_aAlmarinez, Mherby C. _eauthor
700			_aAngkahan, Dawn Gabrielle D. _eauthor
700			_aBanao, Laureana Joy S. _eauthor
700			_aDela Cruz, Froilan Arnel M. _eauthor
700			_aLeocario, John Christian Z. _eauthor
942			_2lcc _cBTH COE _n0
999			_c30464 _d30464