000			02149nam a22003735i 4500
001			20898504
003			OSt
005			20240805104731.0
008			190321s2019 nju 000 0 eng
010			_a 2019937605
020			_a9780135732410 (pbk. : alk. paper)
040			_aDLC _beng _erda _cTUPM
042			_apcc
050		0	_aTK 7874.75 _bD55 2019
100	1		_aDillinger, Thomas E.
245	0	0	_aVlsi design methodology development / _cThomas E. Dillinger.
250			_a1st edition.
263			_a1907
264		1	_aHoboken, NJ : _bPearson Education, Inc., _c2019.
300			_a xvii, 734 pages : _billustrations ; _c24 cm
336			_atext _btxt _2rdacontent
337			_aunmediated _bn _2rdamedia
338			_avolume _bnc _2rdacarrier
504			_aIncludes index and bibliographical references
505	0		_aIntroduction VLSI Design methodology Hierarchical design decomposition Cell and IP modeling Characteristics of functional validation Characteristics of formal equivalency verification Logic synthesis Placement Routing Layout parasitic extraction and electrical modeling Timing analysis Noise analysis Power analysis Power rail voltage drop analysis Electromigration (EM) reliability analysis Miscellaneous electrical analysis requirements ECOs Physical design verification Design for testability analysis Preparation for tapeout Post-silicon debug and characterization ("bring-up") and product qualification
520			_aAs microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.
650	1	0	_aIntegrated circuits _xVery large scale integration
650	1	0	_aIntegrated circuits
650	1	0	_aMicroelectronics
906			_a0 _bibc _corignew _d2 _eepcn _f20 _gy-gencatlg
942			_2lcc _cBK
999			_c3597 _d3597