Design of pvt (process, voltage, and temperature) variation- less i/o buffer using skywater 130nm cmos (complementary metal-oxide-semiconductor) process for usb (universal serial bus) applications/ Rafael Carlos M. Adan, Mherby C. Almarinez, Dawn Gabrielle D. Angkahan, Laureana Joy S. Banao, Froilan Arnel M. Dela Cruz, and John Christian Z. Leocario.--

Bachelor's thesis

College of Engineering.-- Bachelor of science in electronics engineering: Technological University of the Philippines, 2025.

Includes bibliographic references and index.

This paper presents the design of a Process, Voltage, and Temperature (PVT)
variation-resilient Input/Output (I/O) buffer using the Skywater 130nm CMOS technology
for USB applications. PVT variations often degrade I/O buffer performance, affecting
signal integrity, power efficiency, and reliability. To address these challenges, the proposed
design integrates PVT detection and compensation techniques, ensuring consistent
operation under fluctuating conditions. The buffer supports a maximum data rate of 50
MHz and achieves a data throughput of 100 Mbps. Silicon measurement results confirm
reliable operation at a load capacitance of 20 pF and VDDIO supply voltages of 1.8V and
2.5V. The analysis of the compensated and uncompensated circuits reveals a clear
advantage for the compensated design. The compensated circuit achieved a higher mean
slew rate of 1.1352 V/ns compared to 0.9439 V/ns for the uncompensated circuit,
indicating an improved dynamic response. Furthermore, the distribution of slew rates in
the compensated circuit is more tightly clustered around the optimal range of 1.0–1.2 V/ns,
as evidenced by a lower standard deviation of 0.2386 V/ns versus 0.2784 V/ns in the
uncompensated circuit. This consistent performance highlights the effectiveness of the
compensation techniques implemented in the design maintaining stability across various
PVT variations. The buffer’s architecture offers a robust and power-aware solution suitable
for high-speed digital interfaces, particularly in systems where maintaining data integrity
under variable environmental and manufacturing conditions is critical. This work
contributes a practical and efficient approach to designing reliable I/O buffers for modern
integrated circuits, especially in USB and other high-speed communication domains where
PVT robustness is increasingly essential.