Vlsi design methodology development / Thomas E. Dillinger.

Includes index and bibliographical references

Introduction VLSI Design methodology Hierarchical design decomposition Cell and IP modeling Characteristics of functional validation Characteristics of formal equivalency verification Logic synthesis Placement Routing Layout parasitic extraction and electrical modeling Timing analysis Noise analysis Power analysis Power rail voltage drop analysis Electromigration (EM) reliability analysis Miscellaneous electrical analysis requirements ECOs Physical design verification Design for testability analysis Preparation for tapeout Post-silicon debug and characterization ("bring-up") and product qualification

As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.